Protection circuit for extending headroom with off-chip inductors

ABSTRACT

A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the circuit to swing above and below the bias voltage. A protection circuit is included, either on-chip or off-chip, to protect the integrated circuit components if there is a fault condition in either of the off-chip impedances.

CROSS-REFERENCE TO OTHER APPLICATIONS

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/221,617, filed Jul. 28, 2000, and further is acontinuation-in-part of U.S. application Ser. No. 09/897,601, filed Jul.3, 2001, which itself claims the benefit of U.S. Provisional ApplicationNo. 60/215,850, filed Jul. 3, 2000, and U.S. Provisional Application No.60/221,617, filed Jul. 28, 2000, all of which are incorporated herein intheir entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention generally relates to variable gain amplifiers andapplications of the same. In an embodiment, the variable gain amplifieris used in a set-top control box for the delivery of cable televisionservice to a customer. In another embodiment, the variable gainamplifier is used in a cable modem.

[0004] 2. Related Art

[0005] In modern sub-micron semiconductor processes, power supplyvoltages continue to be reduced. In an example used herein, the powersupply voltage is 3.3V. This is less than the more common value of 5Vused by most bipolar processes. More recent complementarymetal-oxide-semiconductor (CMOS) processes operate at 1.2V. Because ofthis reduced power supply voltage, it is no longer possible to “stack”transistors on top of one another to improve bandwidth and linearity.There is simply not enough voltage dynamic range. In fact, even a simpledifferential amplifier may not have enough dynamic range to operateproperly when the signals at the output have large amplitudes.

[0006] The need for very good linearity is even more striking when theinput to the chip is single-ended, rather than differential. Thisrequires even more dynamic range at the output of the amplifier. Beingable to apply single-ended signals to the chip avoids the cost of anexternal balun transformer. What is needed is a system and method forimproving the dynamic range of an amplifier while providing protectionto the on-chip components.

SUMMARY OF THE INVENTION

[0007] This invention uses external surface mount inductors or surfacemount ferrite beads to connect the output nodes of multiple differentialamplifiers to V_(DD) (the positive power supply). The external inductorsor ferrites provide a short-circuit at DC and a high impedance over arange of operating frequencies (e.g., 50-860 MHz). This allows for muchgreater dynamic range on the internal differential pairs.

[0008] A further feature of this invention is a special on-chip biasingarrangement at the output that prevents damage from occurring to thechip, should one of the above-mentioned inductors or ferrites not beinstalled, or become an open-circuit.

BRIEF DESCRIPTION OF THE FIGURES

[0009]FIG. 1 illustrates an electronic circuit in an embodiment of thepresent invention:

[0010]FIG. 2 illustrates an exemplary Community Antenna Television(CATV);

[0011] FIGS. 3A-3B illustrate two embodiments of the amplifier of FIG.2;

[0012]FIG. 4A illustrates one embodiment of the present inventionwherein the amplifier circuit assembly of FIG. 3A is depicted;

[0013]FIG. 4B illustrates one embodiment of the present inventionwherein the amplifier array of FIG. 3B is depicted;

[0014]FIG. 4C illustrates a typical differential pair amplifier of theamplifier array depicted in FIG. 4B;

[0015]FIG. 5 illustrates a mixer used in an embodiment of the presentinvention;

[0016]FIG. 6 illustrates a typical integrated circuit having adifferential pair amplifier coupled to on-chip impedances;

[0017]FIG. 7 illustrates an integrated circuit having a differentialpair amplifier coupled to on-chip impedances and to off-chip inductors;

[0018]FIG. 8 illustrates an integrated circuit having a differentialpair amplifier coupled to on-chip impedances and to off-chip ferritebeads;

[0019]FIG. 9A illustrates an embodiment of the present invention whereinone ferrite bead has failed;

[0020]FIG. 9B illustrates an embodiment of the present invention whereinboth ferrite beads have failed;

[0021]FIG. 10 illustrates an embodiment of the present invention havinga protection circuit disposed;

[0022]FIG. 11A illustrates an embodiment of the present invention havinga protection circuit disposed thereon, wherein one ferrite bead hasfailed; and

[0023]FIG. 11B illustrates an embodiment of the present invention havinga protection circuit disposed thereon, wherein both ferrite beads havefailed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Looking first at FIG. 1, an exemplary circuit depicting anembodiment of the invention is illustrated. An electronic circuit 102 isseen receiving an input 104. Input 104 can be a single input or adifferential input. Electronic circuit 102 is further connected to abias voltage 106. Bias voltage 106 is shown as V_(DD) and is the commondirect current (DC) voltage for the overall circuit for which electroniccircuit 102 is a part. Electronic circuit 102 is shown having adifferential output comprising a positive output 108 and a negativeoutput 110. One skilled in the art(s) will appreciate, based on theteachings contained herein, that the invention will also apply to anelectronic circuit having a single output. Positive output 108 isconnected to bias voltage 106 through a first impedance 112, andnegative output 110 is connected to bias voltage 106 through a secondimpedance 114. First impedance 112 and second impedance 114 havesubstantially zero DC voltage drop and are substantially an open circuitto signals in the frequency range of interest.

[0025] Looking now to FIG. 2, an example of a community antennatelevision (CATV) system (also referred to as cable television) isshown. A CATV cable 202 is shown connected to a diplexer 204. Diplexer204 includes filters (not shown) that permit upstream channels 212 to bepassed to cable 202 and allow downstream channels 220 to be passed to anamplifier 206. Preferably, for the U.S. and Canada, the up-streamchannels cover from 5-42 MHz and the downstream channels cover from54-860 MHz. Concentrating on the down-stream, the output of amplifier206 is an amplified signal 222 that is routed to a tuner 208. Tuner 208includes at least one bandpass filter that selects a single down-streamchannel 224 having a 6 MHz bandwidth. In embodiments, down-streamchannel 224 is centered at 44 MHz. Down-stream channel 224 is thenrouted to a demodulator 210, which outputs a demodulated signal 218 forfurther processing before being sent to a user device (e.g. televisionset or computer). As an example, and not meant to be limiting,demodulated signal 218 can be digital video or cable modem data.Demodulator 210 also analyzes the power of down-stream channel 224 andoutputs a feedback 216 to control an amplifier (not shown) in tuner 208and outputs a feedback 214 to control amplifier 206.

[0026] In FIG. 3A, an embodiment of amplifier 206 is illustrated.Amplifier 206 is comprised of an amplifier circuit assembly 302 thatreceives downstream channels 220. Amplifier circuit assembly 302 alsoreceives a control signal 306 from a feedback control 304. Feedbackcontrol 304 is controlled by feedback 214. Further details of thepurpose and operation of feedback control 304 and control signal 306 arepresented in U.S. patent application “Extended Range Variable GainAmplifier,” Application Ser. No. 09/897,601, filed Jul. 3, 2001,incorporated herein by reference in its entirety. Amplifier circuitassembly 302 outputs amplified signal 222.

[0027] A second embodiment is illustrated in FIG. 3B. Amplifier 206 isshown comprising an amplifier array 310 and an automatic gain control(AGC) logic decoder 312. Amplifier array receives downstream channels220 and outputs amplified signal 222. Amplifier array 310 also receivesAGC control signal 314 from AGC logic decoder 312 under the control offeedback 214. Further details of the purpose and operation of AGC logicdecoder 312 and AGC control signal 314 are presented in U.S. patentapplication “Extended Range Variable Gain Amplifier,” Application Ser.No. 09/897,601, filed Jul. 3, 2001, incorporated herein by reference inits entirety.

[0028] Amplifier circuit assembly 302 is illustrated in FIG. 4A ascomprising a differential pair amplifier 402 having a positive amplifiedsignal 222(P) and a negative amplified signal 222(N). Within amplifiercircuit assembly 302, positive amplified signal 222(P) is seen beingconnected to V_(DD) through a first load inductor 404 and a first loadresistor 408 (illustrated as LL1 and LR1, respectively), and negativeamplified signal 222(N) is seen being connected to V_(DD) through asecond load inductor 406 and a second load resistor 410 (illustrated asLL2 and LR2, respectively). External to amplifier circuit assembly 302,positive amplified signal 222(P) is shunted through a first impedance412 to V_(DD) and negative amplified signal 222(N) is shunted through asecond impedance 414 to V_(DD). First impedance 412 and second impedance414 are selected such that they provide substantially zero impedance toDC voltage and provide a substantially high impedance to signals in thefrequency range of interest. In an embodiment, amplifier circuitassembly 302 is disposed on a common integrated circuit (IC) substrateand first impedance 412 and second impedance 414 are mounted external tothe common substrate.

[0029] Amplifier array 310 is further illustrated in FIG. 4B. Downstreamchannels 220 are accepted by amplifier array 310 and routed to each of aplurality of differential pair amplifiers 416(1) through 416(n). In animplementation, some inputs can be attenuated through a resistor ladder(typically on-chip). The output of any differential pair amplifier416(i) is a differential pair output signal 417(i). Differential pairoutput signal 417(1) through 417(n) are routed to a combiner 418. In oneembodiment, combiner 418 is a summer. Combiner 418 combines differentialpair output signals 417(i) and outputs positive amplified signal 222(P)and negative amplified signal 222(N). Positive amplified signal 222(P)is seen being connected to V_(DD) through a first load inductor 420 anda first load resistor 424 (illustrated as LL1 and LR1, respectively),and negative amplified signal 222(N) is seen being connected to V_(DD)through a second load inductor 422 and a second load resistor 426(illustrated as LL2 and LR2, respectively). External to amplifier array310, positive amplified signal 222(P) is shunted through a firstimpedance 428 to V_(DD) and negative amplified signal 222(N) is shuntedthrough a second impedance 430 to V_(DD). First impedance 428 and secondimpedance 430 are selected such that they provide substantially zeroimpedance to DC voltage and provide a substantially high impedance tosignals in the frequency range of interest. In an embodiment, amplifiercircuit assembly 310 is disposed on a common integrated circuit (IC)substrate and first impedance 428 and second impedance 430 are mountedexternal to the common substrate.

[0030] A representative amplifier circuit assembly 401 is illustrated inFIG. 4C. Nodes 432 and 434 illustrate the combining of the plurality ofdifferential pair output signals 417(i), wherein node 432 is thepositive node outputting positive amplified signal 222(P) and node 434is the negative node outputting negative amplified signal 222(N).

[0031]FIG. 5 illustrates an alternate embodiment of the invention. InFIG. 5, a mixer 506 is illustrated receiving an input signal 502 and amixing signal 504. Mixer 506 outputs a mixed output signal 508. Mixedoutput signal 508 is connected through an impedance 510 to V_(DD).Impedance 510 is selected such that it provides substantially zeroimpedance to DC voltage and provides a substantially high impedance tosignals in the frequency range of interest. Mixed output signal 508 isshown as being a single output. Those skilled in the relevant art(s)will appreciate, based on the teachings contained herein, that theinvention with respect to the mixer embodiment also applies to theimplementation wherein mixed output signal 508 is a differential output.

[0032] The circuits shown in FIGS. 4A-4C illustrate downstream channels220 as being a single input signal. The invention also applies to theimplementation wherein downstream channels 220 is a differential input,as will be understood by those skilled in the art(s), based on theteachings contained herein.

[0033]FIG. 6 illustrates an example of amplifier circuit assembly 302and representative amplifier circuit assembly 401. FIG. 6 depicts atypical integrated circuit 602 as comprising a differential pair 604, afirst load inductor 606, a first load resistor 610, a second loadinductor 608, and a second load resistor 612. Differential pair 604further comprises a pair of transistors 614 and 616. Transistors 614 and616 have a common source tied to V_(SS). Transistor 614 is shownaccepting a positive input signal 601(P) and transistor 616 is shownaccepting a negative input signal 601(N). Transistor 614 is shown havinga negative output 603(N) and transistor 616 is shown having a positiveoutput 603(P). Negative output 603(N) is connected through first loadinductor 606 and first load resistor 610 to V_(DD) and positive output603(P) is connected through second load inductor 608 and second loadresistor 612 to V_(DD).

[0034]FIG. 7 expands on FIG. 4A and FIG. 4C and illustrates anintegrated circuit connected according to an embodiment of the presentinvention. Amplifier circuit assembly 302;401 is comprised of on-chipresistors and inductors (shown as R1, R2, L1, and L2 in FIG. 7), anddifferential pair amplifier 402;416 receiving differential downstreamchannels 220(P) and 220(N). Differential pair amplifier 402;416 isfurther comprised of transistors receiving differential downstreamchannels 220(P) and 220(N) at their respective gates, further configuredwith a common source connected to V_(SS), and having the output signals222(N) and 222(P) found at the drain. Output signal 222(P) is connectedthrough first impedance 412;428 to VDD, and output signal 222(N) isconnected through second impedance 414;430 to VDD. In this embodiment,first impedance 412;428 and second impedance 414;430 are shown asinductors, although other impedances (such as those that provide asubstantially short circuit to DC voltage while being a high impedanceto signals in the frequency range of interest) may be used, as will beapparent to those skilled in the art(s). Further, the components ofamplifier circuit assembly 302;401 are preferably mounted on a common ICsubstrate, whereas first impedance 412;428 and second impedance 414;430are preferably mounted external to the common substrate.

[0035]FIG. 8 expands on FIG. 4A and FIG. 4C and illustrates anintegrated circuit connected according to a second embodiment of thepresent invention. Amplifier circuit assembly 302;401 is comprised ofon-chip resistors and inductors (shown as R1, R2, L1, and L2 in FIG. 7),and differential pair amplifier 402;416 receiving differentialdownstream channels 220(P) and 220(N). Differential pair amplifier402;416 is further comprised of transistors receiving differentialdownstream channels 220(P) and 220(N) at their respective gates, furtherconfigured with a common source connected to V_(SS), and having theoutput signals 222(N) and 222(P) found at the drain. Output signal222(P) is connected through first impedance 412;428 to VDD, and outputsignal 222(N) is connected through second impedance 414;430 to VDD. Inthis second embodiment, first impedance 412;428 and second impedance414;430 (which are shown as inductors in FIG. 7) are shown as ferritebeads, although the invention is not limited to this embodiment, as willbe apparent to those skilled in the art(s). Further, the components ofamplifier circuit assembly 302;401 are preferably mounted on a common ICsubstrate, whereas first impedance 412;428 and second impedance 414;430are prerably mounted external to the common substrate.

[0036] In the following discussion, values have been selected toillustrate the present invention. These values of voltage, resistance,inductance, and current are provided for purposes of illustration only.They are not meant to be limiting.

[0037] In the circuit of FIG. 8, wherein the outputs of the amplifiercircuit assembly are connected through the external ferrite beads toV_(DD), and for the example where V_(DD) is 3.3 volts, the DC currentflowing through the ferrite beads (i_(F1) and i_(F2)) is 49.3 mA, andthe DC current flowing through the on-chip spiral inductors (i_(S1) andi_(S2)) is zero amps. In FIG. 9A, a circuit is shown for the examplewherein the ferrite beads have a minimum inductance of 1 μH and theon-chip spiral inductors have a value of 10 nH with a total seriesresistance of 50 Ω. In FIG. 9A, one of the beads has failed and is opencircuited, and thus i_(F2) is 0 amps. As a result of the bead failing,i_(F1) will be 59.7 mA, i_(S2) will be 38.4 mA, and i_(S1) remains at 0mA. The value of i_(S2) of 38.4 mA exceeds the desired design limit ofthe spiral inductor, and may damage the entire chip.

[0038] In FIG. 9B, the example wherein both ferrite beads have failed isshown. In this example, both i_(F1) and i_(F2) will be 0 mA, whilei_(S1) and i_(S2) will be 47.2 mA. Again, this current exceeds thedesired design limit of the spiral inductor, and may damage the chip.What is needed is an enhancement to the circuit that will keep is, andi_(S2) below the desired design limit of the spiral inductor.

[0039] Looking now to FIG. 10, an alternate embodiment of the presentinvention is illustrated. An on-chip resistor 1002 is connected betweena common node of first load inductor 404;420 and second load inductor406;422 and V_(DD). An exemplary value for on-chip resistor 1002 is 150Ω. Also connected to the same node is an on-chip capacitor 1004. On-chipcapacitor 1004 is further connected to a potential that is substantiallyequal to ground at the frequency range of interest. In this example,i_(F1) and i_(F2) will be 49.3 mA, while i_(S1), i_(S2), and i_(R) willbe 0 mA.

[0040] Looking now to FIG. 11A, the condition wherein one ferrite beadfails is shown. In this example, i_(F2) will be 0 mA, while i_(F2) willbe 91.3 mA, i_(S2) will be 24.6 mA, i_(S1) will be 18.4 mA (in thedirection shown by the arrow), and i_(R) will be 6.1 mA. Thus, themaximum current flowing through either inductor will be 24.6 mA, whichis within the desired design limit of the spiral inductor. As a result,if a single ferrite bead fails, the addition of on-chip resistor 1002and on-chip capacitor 1004 will protect the chip from damage.

[0041] In FIG. 11B, the condition wherein both ferrite beads fail isshown. In this example, i_(F1) and i_(F2) will be zero and i_(S1) andi_(S2) will be 9.2 mA. The current through on-chip resistor 1002 will be18.4 mA. Thus, the maximum current flowing through either inductor willbe 9.2 mA, which is within the desired design limit of the spiralinductor. As a result, if both ferrite beads fail, the addition ofon-chip resistor 1002 and on-chip capacitor 1004 will protect the chipfrom damage.

[0042] In each of the examples given above, the values are provided forpurpose of illustration and not limitation. One skilled in the relevantart(s) will understand, based on the teachings contained herein, that achange in the value of the bias voltage will result in a change in thevalues of the currents through the components of the circuits. Further,the value of the on-chip resistor is provided for purpose ofillustration and not limitation, and other values of resistance can beused without deviating from the spirit and intent of the invention.These alternate values of resistance would also change the currentsthrough the various components of the circuit.

[0043] It should be understood that the invention also covers theembodiment wherein on-chip resistor 1002 and on-chip capacitor 1004 areadded to the circuit in an off-chip configuration. Similarly, theinvention also covers the embodiment wherein first impedance 412;428 andsecond impedance 414;430 are fabricated on the substrate along with theamplifier circuit.

[0044] Conclusion

[0045] Benefits of the present invention are, at least, and by way ofexample and not limitation, the following:

[0046] Use of inexpensive external components (surface mount ferrites orinductors) which raise the DC voltage on each gain stage output, whilehaving little or no effect on AC performance.

[0047] The inclusion of an internal resistor-capacitor circuit thatcauses the currents and voltages inside the chip to be reduced, thusavoiding damage to the chip, should one or both of the external ferritesor inductors be missing.

[0048] Little change to original internal circuitry of the chip isrequired, with the exception of a simple resistor-capacitor circuit toprevent damage.

[0049] No common mode output voltage control circuits are required. Theoutputs are always connected to V_(DD).

[0050] Ferrites or inductors allow the output voltage to swing above andbelow the bias voltage for more dynamic range.

[0051] This application can be used with cable modems, TV tuners, andsettop boxes.

[0052] This chip is a variable gain, low noise amplifier with aspecified input match.

[0053] While various embodiments of the present invention have beendescribed above, it should be understood that they have been presentedby way of example only, and not limitation. For example, while theinvention has been described in terms of differential pair amplifiers,one skilled in the art would recognize that the instant invention couldbe applied to single output amplifiers. It will be understood by thoseskilled in the art that various changes in form and details can be madetherein without departing from the spirit and scope of the invention asdefined in the appended claims. Thus, the breadth and scope of thepresent invention should not be limited by any of the above-describedexemplary embodiments, but should be defined only in accordance with theclaims and their equivalents.

What is claimed is:
 1. An electronic circuit assembly, comprising: anelectronic circuit, a first impedance, and a second impedance, whereinsaid electronic circuit has a positive output connected to a biasvoltage through said first impedance, and a negative output, connectedto said bias voltage through said second impedance; and said positiveoutput further being connected to said bias voltage through a firstoff-chip impedance and said negative output further being connected tosaid bias voltage through a second off-chip impedance.
 2. The electroniccircuit assembly of claim 1, wherein the electronic circuit is anamplifier.
 3. The electronic circuit assembly of claim 2, wherein theamplifier is comprised of an amplifier circuit assembly, said amplifiercircuit assembly having a positive amplifier output and a negativeamplifier output, said positive amplifier output being said positiveoutput and said negative amplifier output being said negative output. 4.The electronic circuit assemble of claim 2, wherein the amplifier iscomprised of a plurality of amplifier circuit assemblies, each of saidplurality of amplifier circuit assemblies having a positive amplifieroutput and a negative amplifier output, each said positive amplifieroutput being combined into said positive output and each said negativeamplifier output being combined into said negative output.
 5. Theelectronic circuit assembly of claim 1, wherein said first impedancecreates an first alternating current load, and said second impedancecreates a second alternating current load.
 6. The electronic circuitassembly of claim 5, wherein said first impedance is comprised of afirst inductor and a first resistor, and said second impedance iscomprised of a second inductor and a second resistor.
 7. The electroniccircuit assembly of claim 5, wherein said first impedance is comprisedof a first resistor, and said second impedance is comprised of a secondresistor.
 8. The electronic circuit assembly of claim 5, wherein saidelectronic circuit is disposed on a common substrate, and, further, saidfirst impedance and said second impedance are disposed on said commonsubstrate.
 9. The electronic circuit assembly of claim 8, wherein saidfirst off-chip impedance results in substantially zero direct currentvoltage drop between said bias voltage and said positive output of saidelectronic circuit while appearing as a substantially open circuit tosignals having frequencies within a desired operating frequency range,and said second off-chip impedance results in substantially zero directcurrent voltage drop between said bias voltage and said negative outputof said electronic circuit while appearing as a substantially opencircuit to signals having frequencies within said desired operatingfrequency range.
 10. The electronic circuit assembly of claim 8, whereinsaid first off-chip impedance is a first off-chip inductor, and saidsecond off-chip impedance is a second off-chip inductor.
 11. Theelectronic circuit assembly of claim 8, wherein said first off-chipimpedance and said second off-chip impedance are surface mountedexternal to said common substrate.
 12. The electronic circuit assemblyof claim 1, wherein said first off-chip impedance is a first ferritebead and said second off-chip impedance is a second ferrite bead. 13.The electronic circuit assembly of claim 10, further comprising a commonpoint resistor, wherein said common point resistor has a first port anda second port, said first port being connected to a first potential, andwherein said positive output of said electronic circuit is connectedthrough said first impedance to said second port of said common pointresistor and said negative output of said electronic circuit beingconnected through said second impedance to said second port of saidcommon point resistor.
 14. The electronic circuit assembly of claim 13,wherein a direct current voltage drop across said common point resistoris substantially equal to zero when said first off-chip impedance andsaid second off-chip impedance are in normal operation.
 15. Theelectronic circuit assembly of claim 14, wherein a direct-currentcurrent through said common point resistor is substantially non-zerowhen either one or both of said first off-chip impedance and said secondoff-chip impedance are in a fault condition.
 16. The electronic circuitassembly of claim 13, wherein said first potential is said bias voltage.17. The electronic circuit assembly of claim 13, wherein said commonpoint resistor is disposed on said common substrate.
 18. The electroniccircuit assembly of claim 13, wherein said second port of said commonpoint resistor is further connected through a common capacitor to asecond potential.
 19. The electronic circuit assembly of claim 18,wherein said second potential is substantially equal to a ground at adesired operating frequency range.
 20. The electronic circuit assemblyof claim 18, wherein said common capacitor is disposed on said commonsubstrate.
 21. An circuit for amplifying a signal, comprising: asubstrate, a plurality of gain stages, wherein each gain stage of saidplurality of gain stages has a positive output and a negative output,each said positive output being combined into a combined positive outputand each said negative output being combined into a combined negativeoutput, said combined positive output being connected to a second portof a common point resistor through a first impedance and said combinednegative output being connected to said second port of said common pointresistor through a second impedance, wherein a first port of said commonpoint resistor is connected to a first potential, said first impedancebeing a first inductor and a first resistor disposed on said substrateand said second impedance being a second inductor and a second resistordisposed on said substrate, said combined positive output further beingconnected to said bias voltage through a first off-chip impedance andsaid combined negative output further being connected to said biasvoltage through a second off-chip impedance, whereby said first off-chipimpedance and said second off-chip impedance raises a direct currentvoltage on said positive output and on said negative output of each saidgain stage while having little or no effect on alternating currentperformance.
 22. The circuit of claim 21, wherein said first potentialis a bias voltage.
 23. The circuit of claim 22, further comprising acommon point capacitor disposed between said second port of said commonpoint resistor and a second potential.
 24. The circuit of claim 23,wherein said second potential is substantially equal to an alternatingcurrent ground.
 25. The circuit of claim 23, wherein an output of saidcircuit swings above and below said bias voltage for additional dynamicrange.
 26. The circuit of claim 21, wherein said first off-chipimpedance and said second off-chip impedance are ferrite beads.
 27. Amethod for extending dynamic range of an output of an amplifier, theamplifier comprising a plurality of gain stages, each of the pluralityof gain stages having a positive output and a negative output, whereinthe positive outputs are combined to create a combined positive outputand the negative outputs are combined to create a combined negativeoutput, and further wherein a first on-chip impedance is connectedbetween the combined positive output and a bias voltage of the amplifierand a second on-chip impedance is connected between the combinednegative output and the bias voltage, comprising the steps of: (1)connecting a first off-chip impedance between the combined positiveoutput of the gain stages and the bias voltage; and (2) connecting asecond off-chip impedance between the combined negative output of thegain stages and the bias voltage.
 28. The method of claim 27, furthercomprising the steps of: (3) connecting a common resistor between saidbias voltage of said amplifier and a resistor port, wherein saidresistor port is further connected to the first on-chip impedance andthe second on-chip impedance; and (4) connecting a common capacitorbetween said resistor port and a ground.
 29. The method of claim 28,wherein the first on-chip impedance is a first reactive load and thesecond on-chip impedance is a second reactive load.
 30. The method ofclaim 27, wherein at least one of said first off-chip impedance and saidsecond off-chip impedance is a ferrite bead.
 31. A method of protectingan electronic circuit assembly from over-current damage, wherein theelectronic circuit assembly is comprised of an electronic circuit havingan output, the output being connected through an on-chip impedance tocreate a circuit assembly output, comprising the steps of: (1) disposinga protection impedance between a first potential and a protectionimpedance port, said protection impedance port being connected to thecircuit assembly output of the electronic circuit assembly; (2)disposing a capacitor between said protection impedance port and asecond potential, wherein said second potential is substantially equalto an alternating current ground; and (3) connecting the output of theelectronic circuit through one or more off-chip impedances to the firstpotential, said off-chip impedances causing a current through theon-chip impedance to be substantially zero in a normal operatingcondition.
 32. The method of claim 31, wherein the electronic circuitassembly is further comprised of a plurality electronic circuits, eachof said plurality of electronic circuits having an output, wherein allof said outputs are combined to create a combined output, said combinedoutput being connected through an on-chip impedance to create saidcircuit assembly output.
 33. The method of claim 31, wherein each ofsaid one or more off-chip impedances presents substantially zeroimpedance to a direct current voltage and presents a high impedance tosignals within a frequency range of interest.
 34. The method of claim31, wherein each of said one or more off-chip impedances is a ferritebead.
 35. An electronic circuit assembly, comprising: an electroniccircuit, and an on-chip impedance, wherein said electronic circuit hasan output connected to a bias voltage through said on-chip impedance,and said output further being connected to said bias voltage through anoff-chip impedance.
 36. The electronic circuit assembly of claim 35,wherein the electronic circuit is an amplifier.
 37. The electroniccircuit assembly of claim 36, wherein the amplifier is comprised of aplurality of amplifier circuit assemblies, each of said plurality ofamplifier circuit assemblies having an amplifier output, each saidamplifier output being combined into a combined output, said combinedoutput being said output of said electronic circuit.
 38. The electroniccircuit assembly of claim 35, wherein said on-chip impedance iscomprised of an inductor and a resistor.
 39. The electronic circuitassembly of claim 38, wherein said electronic circuit is disposed on acommon substrate, and, further, said on-chip impedance is disposed onsaid common substrate.
 40. The electronic circuit assembly of claim 38,wherein said off-chip impedance is an off-chip inductor.
 41. Theelectronic circuit assembly of claim 39, wherein said off-chip impedanceis mounted external to said common substrate.
 42. The electronic circuitassembly of claim 35, wherein said off-chip impedance is a ferrite bead.43. The electronic circuit assembly of claim 40, further comprising acommon point resistor, wherein said common point resistor has a firstport and a second port, said first port being connected to said biasvoltage, and said second port being connected through said impedance tosaid output of said electronic circuit.
 44. The electronic circuitassembly of claim 43, wherein said second port of said common pointresistor is further connected through a common capacitor to a secondpotential, wherein said second potential is substantially equal to aground at a desired operating frequency range.
 45. The electroniccircuit assembly of claim 44, wherein said common point resistor andsaid common capacitor are disposed on said common substrate.
 46. Theelectronic circuit assembly of claim 36, wherein said amplifier is usedin a cable modem.
 47. The electronic circuit assembly of claim 36,wherein said amplifier is used in a set-top box.
 48. The electroniccircuit assembly of claim 36, wherein said amplifier is used in atelevision tuner.